Electronic devices face continued pressure to design and produce their configurations to a further state of miniaturization, ergonomically pleasing shapes, and a reduced weight. To achieve these goals, substrates must be thinned to 100 um (microns) and less, making them extremely fragile and difficult to handle with existing equipment. To prevent breakage, cracking, or otherwise chipping and stressing these fragile substrates, it becomes necessary to always keep them temporarily supported by an external platform, being a rigid carrier or a membrane. During microelectronic manufacturing, the thinned substrates are temporarily supported by rigid carriers, as these provide the most secure and reliable media to conduct high-resolution processes. These carrier substrates may be composed of sapphire, quartz, certain glasses, or silicon and exist in thicknesses from 0.5-1.5 mm (millimeters=500-1,500 um). The device substrate is commonly affixed to the carrier by an adhesive that offers sufficient adhesive force and quality to withstand the manufacturing process, while also allowing the thinned substrate to be removed at the completion of work without damage to its integrity.
Common tape adhesives exist which offer temporary support to the device substrate either alone or used as an interface to the carrier. These materials are commonly used for dicing operations, including high-volume photodegradative delamination practices (i.e. pick-and-place). However, tape adhesives are reserved only for the end of the process where dicing occurs. Most tape adhesives are not used in upstream microelectronic processes as their properties do not meet the needs for fabrication, including rigidity and uniformity, thermal and chemical resistance, and outgassing (weight loss). These shortcomings in adhesive tapes result in loss of adhesion, gas bubbles lodged in-between the device substrate and carrier, or produce unwanted gaseous by-products of degradation that adversely interact with the processes of vacuum deposition or etching to produce inferior results.
In the example where thinned substrates include semiconductor wafers, the device substrate is commonly removed from a carrier support, cleaned, and mounted to a film frame containing tape adhesive, allowing the dicing process to proceed. Carrier removal is conducted with robotic assisted complex tooling. Tooling is designed according to the type of adhesive chosen. At the time of this invention, there are no less than six (6) adhesive materials on the market. The majority of these adhesives require a single wafer tooling configuration whereby the tool handles one wafer at a time.
In semiconductor operations, single wafer processes that use thermoplastic adhesives may utilize thermo-mechanical demounting as taught by Thallner in U.S. Pat. Nos. 6,792,991 B2 (2004) and 2007/0155129 (2007). Device wafer separation is achieved by heating the mounted stack to a temperature above the melting point of the thermoplastic adhesive while simultaneously applying a shear force in a manner designed to separate the mounted surfaces. Cleaning with a selected organic solvent typically follows to ensure residual adhesive is cleaned from the substrate.
Another single-wafer tooling practice for removing carrier supports is described in U.S. Patent Application Nos. 2009/0017248 A1 (2009), Larson et al., 2009/0017323 A1 (2009), Webb et al., and in the International Application WO 2008/008931 A1 (2008), Webb et al. The adhesive described is a bilayer system composed of a photothermal conversion layer and a curable acrylate. The applications cite the use of a laser irradiation device which allows rapid demount of the external support carrier and is followed by a mechanical peeling practice of the curable acrylate from the thinned substrate.
Laser ablative carrier demounting practices are demonstrated in microelectronics manufacturing as described in U.S. Pat. No. 6,036,809 (2000) Kelly, et. al, U.S. Pat. No. 7,867,876B2 (2011) and U.S. Pat. No. 7,932,614B2 (2011) Codding, et. al. Laser ablative tooling is non-trivial, in that it requires exacting focus of an optical device of a specific wavelength and to do this onto an interface between the work unit and the carrier substrate. The laser's focus does this while it or the substrate is being shifted in continual motion moving rapidly across the substrate. It is well known to those familiar with the art of coatings and planarization efforts that irregularities will exist in materials applied over the surface of the work unit. The adhesives used for these practices vary between rubber, silicone, polyimide, acrylic, and the like. The laser transmits through an optically clear carrier substrate and focuses onto the interfacial region where the adhesive meets the carrier, causing a significant and immediate rise in temperature which burns the material and destroys the adhesive interface to the carrier. The laser continues rastering to the next location in an apparent smooth fashion until the entire surface of the substrate has been exposed and thereupon the carrier release is expected. The impacts of this process is realized later when irregularities are observed as micro-cracks, fissures, and residue that is burnt onto surfaces which cannot be removed. Laser ablative processes, although a common practice for debonding delicate substrates, remains a subject of much discussion when considered for high volume manufacturing.
These and other carrier debonding (removal) practices are discussed in U.S. Patent Application No. 2009/0218560A1 (2009) Flaim, et. al, where the author consolidates the practice of wafer and carrier separation into four approaches, including: 1) chemical, 2) photodecomposition (laser ablation), 3) thermomechanical, and 4) thermal decomposition. Although the author mentions drawbacks in each mechanism, they refrain from classifying them as single-wafer or batch processing according to their respective tooling configuration. Of these four processes, only chemical penetration is considered as a batch mechanism. In such processes, wafers may be populated into a cassette or holder and immersed into a chemical liquid for a designated time to allow penetration into the adhesive, emulsification, and removal to allow carrier debonding. Chemical diffusion-based debonding may require several hours to complete. At the time of this document writing, common throughput for single wafer processes are scheduled for 20-25 wafers per hour (wph). In the case of a conventional chemical debond where perforated (drilled holes) carriers are used, cassettes of between 12-25 wafers are used where debonding may last up to four (4) hours. For a bath size of >100 liters as common for most fabrication facilities in Asia, this volume can accommodate up to 4 cassettes at a time, providing throughputs between 12-25 wph, exceeding that for single wafer processes (i.e. 12-25 wafers per cassette×4 cassettes=48-100 wafers/4 hrs=12-25 wph). Without being bound to variations of the art of batch processing, this option is needed in fabrication to offer lower cost options for debonding carrier substrates. Therefore, it is a desire to consider options that enable batch wafer processing as a viable and cost effective practice for thin substrate debonding from carriers.
Other semiconductor batch debonding processes are described in U.S. Pat. No. 6,076,585 (2000) Klingbeil, et. al, and U.S. Pat. No. 6,491,083 B2 (2002) De, et. al, where a fixture holding thinned gallium arsenide (GaAs) wafers are removed from sapphire carriers using an immersion chemical practice. In both of these inventions, the fixture is designed to operate with the wafers held horizontally. The fixture has steps machined within it and requires a perforated carrier substrate that is slightly larger in diameter than the device wafer, such that during the debonding operation, the separation of the two substrates occurs by one item landing upon the fixture step while the wafer separates and falls to a lower level of support. Carrier substrates that are machined to be larger in diameter than the work unit and which have perforations (drilled holes) can be costly. For example, enlarged perforated sapphire substrates are a common choice for GaAs work unit wafers, however, these can cost $1,000 or more per unit. In the case of silicon substrates of diameters at 12″ or the projected 18″ (at the time of this writing, plans are projected), carrier wafers are chosen to be dummy type (i.e. same size, shape, and composition of the work unit without the electronic purity). Oversized perforated carriers are cost prohibitive for large diameter silicon as the cost of machining holes (perforations) can fall between factors of 10-100× the cost of conventional dummy sized wafers. It is a desire to avoid the use of oversized perforated carriers as a means to minimize process costs.
Semiconductor batch demounting processes are also described in U.S. Pat. No. 6,601,592 B1 (2003) and U.S. Pat. No. 6,752,160 (2004) Zhengming Chen, where two fixture cassettes work in conjunction with each other in a manner that allows separation of the device wafer from carrier substrates. The inventions describe the batch process separation between device wafer and carrier as conducted such that the top fixture cassette is populated with the mounted wafers whereby during liquid immersion, the chemistry penetrates the adhesive contact to release the two substrates. The top fixture cassette is constructed in a manner to allow only the device wafer pass downwards to the lower fixture cassette during gravity assisted separation, retaining the carrier substrate. The inventions require the sized of the carrier substrate and device wafer to be different, either the device wafer to exhibit a flat edge (i.e. wafer flat) or the carrier substrate to be oversized as compared to the device wafer. In either case, when the process commences and the fixture cassettes are arranged vertically, the oversize carrier is held back within the above fixture cassette while the device wafer travels from the top to the bottom cassette. Device wafers with a flat location were at one-time popular for reasons of reference location when handling and transferring from one process to another. The wafer flat is less desirable as it eliminates valuable device manufacturing realty on the wafer and reduces the number of devices built upon a substrate. Conversely, oversized carrier wafers are cost prohibitive as described earlier in this document. Further and most important, these inventions describe fixture design that requires the device wafer to be separated and released from the carrier substrate and move freely from one fixture cassette to another during liquid chemical immersion processing. It is commonly understood in the practice of thin wafer handling, that at anytime during this work, the device wafer should always be supported and never left to move freely. Consistent device wafer support would minimize irregular bending, vibration, and edge contact that would generate cracks, chipping, and other flaws within a thin wafer. It is a desire to avoid fixtures that require device wafer flat designs or oversized carriers and to avoid fixtures that promote a batch processing practice which allows the device wafer to move freely and subject itself to cracks, flaws, or other signs of breakage.
A unique semiconductor carrier formation and process for separation from the device wafer is described in the International Publication No. WO 210/107851 A2 (International Application No. PCT/US210/027560), Moore, et al, where a carrier substrate is manufactured (formed) directly onto the device wafer in a manner sufficient to support grinding and backside processing and when complete, the materials used to form the carrier are designed to break down in a liquid chemistry cleaning process. Carrier digestion during a cleans process requires a special fixture to support the device wafer without damage and the simultaneous multiple processing of such items during a batch operation. Once the carrier is digested and removed, the device wafer is anticipated to exhibit some level of mobility within the special fixture. The movement of a thin fragile substrate within a mechanical fixture is anticipated to produce cracks, fissures, and other irregularities due to vibration and movement of the liquid. It is a desire to promote a batch process which mandates support of the device wafer during carrier debonding.
The use of porous carriers in processing a work piece is described in U.S. Pat. 7,708,854 B2 (2010) Kroninger et al., where the author discusses the affixing (bonding) the carrier to the work piece and grinding or polishing to desired level followed by chemical diffusion through the porous carrier with chemicals to effect release and separation of the work piece. The claims describe the practice yet suffers from several fundamental aspects that are important for mainstream microelectronics processing. The first aspect is the claim by the author to apply liquid adhesive to the carrier. While the lay reader may not find this to be of critical concern, it should be understood that the majority of microelectronic processing where thin handling is required by a carrier support, the adhesive is always applied to the device substrate. Applying liquid adhesive to the device substrate allows coverage and curing over topography. The protection of the topography by planarizing or flattening this zone will reduce the occurrence of bubbles or voids in and around the topography. Second, the use of vacuum assisted adhesive coating and penetration will result in reduced performance during debond and become a source of contamination. Adhesive is applied as a liquid to the porous carrier and begins to penetrate and fill the pores. Vacuum is applied which pulls the adhesive further into the pores deep inside the carrier. This practice effectively forms a solid composite structure comprising the adhesive and porous carrier. This solid structure discourages effect of chemical fluids on the adhesive and stops the passage of fluid through the porous carrier. Chemical action on the adhesive within the porous carrier actually dissolves slower as compared to a pure solid of adhesive (bulk form of same dimensions). This is due to the fundamental model of plastics and polymers when in exposed to solvent liquids. According to the model, there is a series of steps in dissolving adhesive/polymer/plastic. The steps include: exposure, absorption, swelling, saturation, break-up and passage to bulk fluid, and finally, further reduction in the bulk fluid. Adhesive that is present in the porous carrier begins to absorb solvent, it swells, increase its volume, however, the porous structure limits continued volume expansion. Therefore, the adhesive present in the porous carrier is slow to reach saturation and in turn will even be slower to break-up and enter the bulk solvent. Adhesive present in the pores of the carrier will remain much longer as compared to a pure form bulk adhesive specimen. Third, the author describes the porous carrier to be open (porous, permeable) after bonding (i.e. bonded to work piece). The bottom of the porous carrier is open, not sealed. This condition is not satisfactory for microelectronic processing. Open or porous carriers require excessive pump-down times during vacuum assisted plasma processes. Further, open or porous substrates allow chemical intrusion and become impossible to effectively clean prior to the next process step. In this condition, the porous carrier becomes a serious source of contamination in the fabrication area causing yield reduction and high scrap rates. There is a need for a porous carrier whereby adhesive is not applied directly to its structure, is not vacuum assisted to force adhesive into its pores, and is completely closed (impervious to chemicals) such that the bonded stack will support microelectronic fabrication (backside processing).
There exist compelling arguments to encourage batch process designs with specially designed porous carriers that avoid the high cost of perforated carriers, discourage costly and complex fixtures, control protection and safety to device substrates, and ensures continual support of the device substrate throughout the process. For these reasons and others not mentioned, it is a desire to create a carrier that supports a device substrate during fabrication high volume manufacturing using vacuum assisted handling tools and is able to be exposed to thermal and chemicals and that also debonds rapidly without harm to the device substrate and supports multiple unit operations in a batch process for high throughput and low-cost benefits.